岗位职责
In this role, you will work with software and hardware engineering groups to define the next-generation inter-chip network architecture for high-performance AI chip and AI network. Requirement of the Job * Identifies the challenging problems, and evaluate various solutions for the next-generation of network for AI chip and AI Super Pod. * Gets strong influences on future AI products by advanced architecture design as the excellent interface between software and hardware. * Documents the high-level architecture specification that defines the inter-chip network subsystem for AI chips. * Participation of front-end Implementation of key subsystem. * Strong technical leadership to archive successful delivery of final silicon product. * Works closely with design, system, and verification team.
职位要求
* Minimum Bachelar degree in Computer Science or Electronics Engineering; M.S. or Ph.D. is preferred * Minimum of 8 years (for M.S.) 5 years (for Ph.D.) of experience on computer architecture or network chip design with proven silicon result. AI chip, Switch chip, RDMA, RoCE sub-domain is preferred. * Strong experience in at least one of the following areas is a must: Server level AI chip design. Smart NIC/RDMA/RoCE design. State-of-the-art Switch chip design (12.8T and above). * Hand-on experience of high-speed interface, such as Die to Die, high speed long-reach SerDes, MAC/PCS, FEC is a plus. * Hand-on experience of interconnects in AI domain is a big plus. * Strong knowledge of AI infrastructure and AI network including Scale-up/Scale-out network, and knowledge of LLM inference and training is a big plus. * Good verbal and written skill for communication.
