岗位职责
In this role, you will work with architect, hardware and software engineering groups to provide accurate performance modeling of the next-generation inter-chip network architecture for high-performance AI chip and AI network. * Identifies the challenging problems, and evaluate various architectural solutions for the next-generation of network for AI chip and AI Super Pod. * Gets strong influences on future AI products by advanced architecture and evaluates the new architecture with performance modeling using C, C++, SystemC or other high level description languages. * Provides solid and accurate modeling result and influence the direction of next generation of AI networking. * Focus in the domain of AI chip to chip interconnect subsystem, Scale-up Switch chip, C2C link, and etc. * Participation in defining the micro-architecture of key subsystem. * Works closely with design, software, system, and verification team for the final success of products.
职位要求
* Minimum Bachelor degree in Computer Science or Electronics Engineering; M.S. or Ph.D. degree is preferred. * Minimum of 3 years of experience in the high-level performance modeling or bit accurate modeling, including but not limited to networking, switch chip, Networks-on-Chip (NoC) and SoC. * Hands on experience in software programming language such as C, C++. * Hands on experience in at least one of the following areas is preferred.
- Sophisticated server AI chip.
- Smart NIC/RDMA/RoCE/DPU.
- State-of-the-art Switch chip. * Knowledge in hardware design such as RTL design is a plus. * Hand-on experience of interconnects in AI domain is a big plus. * Strong knowledge of AI infrastructure and AI network including Scale-up/Scale-out network, and knowledge of LLM inference and training is a big plus. * Good verbal and written skill for communication.
