岗位职责
In this role, you will work with software and hardware engineering groups to define the cutting edge of next-generation AI SOC chips for high-performance computing platform in Data Center. · According to SOC architecture, evaluate PCIE subsystem feature requirement include but not limited to PCIE protocol/PPA improvement/SRIOV virtualization etc. · As the PCIE subsystem IP owner, integration and glue logic RTL development for various of complex SOCs, high quality IP deliver with clean Lint/cdc/rdc and timing closure. · Strong problem solving and solution for PCIE design and IP integration, work together with DV owner and Emulation to cover PCIE related features. · Participate in post silicon bring up and PCIE related issue debug.
职位要求
· Minimum of 5 years of experience on PCIE design for proven silicon. · Familiar with PCIE protocol, including physical layer/data link layer/transaction layer. · Familiar with PCIE Gen5/6 or CXL is plus. · Familiar with AMBA bus protocol like AXI/AHB/APB and CDC/RDC design flow.
