岗位职责
In a fast-paced, leading-edge environment with endless possibilities of innovating and learning, you will be responsible for leading and defining timing signoff design methodologies of complex and world class chips/IPs. In this position, your responsibilities may include, but not be limited to: • Defining and implementing signoff methodology for all areas related to timing analysis, Circuit Quality, Extraction and noise glitch analysis； • Developing robust ASIC design and verification methodology to meet performance requirements including PVT corner definition for design convergence, clock uncertainty requirements, timing budgeting, repeater planning, automatic constraints/exceptions generation & management, and other key differentiating capabilities for quality & efficient timing closure； • Working closely with process technology team to understand process characteristics and setting appropriate design constraints to model on-chip variation effects, power-supply variation, process aging and other PV/Si miscorrelation effects in timing analysis flows； • Engaging closely with Design teams to understand the design & convergence challenges and derive methods to provide recipes with a focus on PPA & TAT optimizations； • Developing timing flows, understand design requirements/objectives and develop signoff conditions and milestone checklists appropriate with the design project goals. Work with 3rd party EDA vendors to resolve issues and drive improvements in design convergence and signoff； • Lead full chip timing signoff work, including SDC quality check, timing aware physical implementation guide, timing analysis and signoff.
职位要求
The ideal candidate should exhibit behavioral traits that indicate: • Self-motivator with strong problem-solving skills • Excellent interpersonal skills, including written and verbal communication • Ability to work as part of a team and collaborate in a high-paced atmosphere • Ability to provide technical direction to the team and influence project execution and methodology Qualifications • Mtech/Btech Engineering Degree in field of Electrical, Electronics, Computer Science with 2+/10+ yrs of relevant RTL2GDS experience • Demonstrated ability in areas of Timing analysis, timing convergence, SI/Noise analysis, Signoff quality (PVT, process variation effects, guardbanding, etc), Timing ECOs, Noise modelling, .libs • Expertise and in-depth knowledge of industry standard EDA tools (Timing, Synthesis, P&R) and ASIC design flow is required • Multi-voltage scenarios design handling knowledge is expected. STA closure/convergence execution with Low power design closure is an added advantage • Proficiency in scripting language, such as, Tcl required, perl / Python is a plus
